A replica biased, n-channel metal-oxide-semiconductor field-effect transistor (n-channel MOSFET or NMOS) voltage regulator can be used to regulate the input/output (I/O) supply voltage to a designed value, for example 3 volts (V), to provide supply voltage to I/O circuitry, for example transistor logic circuits. For instance, a “replica” biased voltage regulator may implement one or more NMOS “pass” transistors which each replicate the voltage of a similar type NMOS replica transistor in a current sourcing type regulator. Each of the NMOS pass transistors and the replica transistor may be “similar” transistors, for example by being formed during the same or according to a similar manufacturing process (e.g., processing) and by having the same or substantially the same temperature effects (e.g., dependency) on the voltage drop between the gate and source with similar threshold voltage (VTN) so that when their gates are biased with a same biasing voltage they supply a similar voltage at their source for a similar load (e.g., impedance or resistance).
In replica-biased architecture, a minimum load current is required through the replica NMOS and pass transistors to get accurate regulated voltage. This current can be called a “leaker” current. For instance, the master transistor must be biased to provide a stable output voltage at its source. Similarly, each replica pass transistor must be biased using the gate voltage of the pass transistor, so that its output voltage can settle down to a regulated voltage. The minimum amount of current required to flow through each pass transistor causes an additional power drain for the regulator which is proportional to the number of I/O supply voltages provided, for example for an equal number of I/Os used. For instance, an amount of extra power is required by the voltage regulator for each I/O, which is equal to the voltage provided, for example to be used by an I/O circuit driver, multiplied by the leaker current passing through the pass transistor.
FIG. 1 illustrates a conventional voltage regulator 100. Regulator 100 includes comparator 110 with charge pump 120 and master NMOS 140 in feedback (e.g., voltage Vrep at the source of NMOS 140) and it's source voltage is fed through a voltage divider to the inverted input IN 1 of comparator 110 and compared with bias voltage “bg” 112 which is provided at the non-inverting input IN 2. The output of comparator 110 is fed through inverter 160 to the gate of transistor 162. The drain of transistor 162 is fed by current mirror 170. Current mirror 170 includes similar transistor 172 and 174 each having their gate biased by current bias/source “ibg” 176. The drain of transistor 174 is also biased by ibg 176. The drain of transistor 172 is tied to the source of transistor 162. The drain of transistor 162 is tied to the gate of NMOS 140 and the current output of charge pump 120. Charge pump 120 is biased by ibg 122. A filter capacitor C 1 is in parallel between charge pump 120 and the gate of NMOS 140. The gate of NMOS 140 is coupled to the gates of NMOS pass or replica transistors 142, 144, 146, and 148. The sources of NMOS transistors 142 through 148 each supply an I/O supply voltage, for example to IO 152 (e.g., an I/O) through 158, respectively. Similarly, resistor R 3 is coupled between the source of each of pass transistors 142 through 148 and ground. Each of I/O 152 through 158 may be described as a transistor logic circuit such as a circuit including low voltage complementary MOSFET (LVCMOS) circuitry.
A bias voltage “bg” may represent a stable bias voltage as known in the industry, for example one provided by circuitry including a bandgap reference or like source. Also, “bg” may represent a stable and/or accurate reference voltage, for example a voltage of 1.2 V plus or minus 3-5 percent. Similarly, a bias current “ibg” may represent a stable bias current as known in the industry, for example one provided by circuitry including a bandgap reference. Also, “ibg” may represent a stable and/or accurate reference current, for example a current of I Amps plus or minus 7-10 percent.
The feedback structure of regulator 100 generates gate voltage VG to drive replica NMOS 140 as well as pass transistors 142 through 148. Each NMOS pass transistor is used to supply supply voltage Vout to each I/O. The “size” of each pass transistor is mainly determined by the input/output (I/O), high output current (IOH), high output voltage (VOH), and/or IOH/VOH specification of I/O. For instance, the “size” of a pass transistor or replica transistor may describe a number of discrete (e.g., single) transistors in parallel and the physical size (e.g., top perspective geographic area or space of a substrate, wafer or integrated circuit (IC) required for the transistor), electrical characteristics, range of VTN, range of current flow of each such discrete transistors. A ratio of current may flow through the master transistor and each replica pass transistor to maintain each output voltage Vout at it's source (e.g., Vout equal to Vrep at the source of master NMOS 140). For example, the amount of current flowing through each pass transistor may be equal to 1 times, 2 times, 3 times, . . . another integer times the amount of current flowing through NMOS 140. This current ratio is determined by the “size” ratios of the replica transistor as compared to each master transistor. For example, with all other size factors equal, if the number of discrete transistors for a pass transistor is increased by tenfold (10×) then the pass transistor can deliver current tenfold (10×) of the master transistor with maintaining an output voltage of the master transistor equal to that of the pass transistor.
One problem with the voltage regulator of FIG. 1 is that as the DC current through each I/O (e.g., I/O 152 through 158) may be zero during operation, when the output of IO is settled (e.g., settles, such as by, after an initialization period after being powered on, reaching a stable level or substantially equal level over time) in its designed or desired high or low voltages, it is necessary to drain a minimum current (leaker current) through each pass transistor, other than using the IO's, to maintain a stable voltage output at the source of each pass transistor that is equal to Vrep. Specifically, as shown in FIG. 1, in order to have the same output that Vout compared to (e.g., having a ratio with) Vrep, a considerable value of “leaker” current is needed at ILeaker 15. It can be appreciated that ILeaker 15 may be divided and provided for each IO. As shown, the leaker current is equal to Vout/R 3 for each I/O. For the design of FIG. 1, R 3 is equal to “R/4”, where “R” is the same resistance as that between the source of NMOS 140 and ground (e.g., R 1+R 2). Thus, ILeaker 15 is equal or in multiples to the current flowing out of the source of NMOS 140. The value of ILeaker 15 causes high currents, which drain or consume power. This power is inversely proportional to the size of “R”. However, increasing resistance “R” to reduce current is very sensitive. For instance, use of a MOS based resistor for “R” cannot meet the accuracy requirements for the resistance of “R” required by the voltage regulator. Thus, for a substrate, wafer or IC based resistor, as resistance “R” increases, so does the amount silicon or physical size required for the resistor providing resistance “R”. The physical size of R can be substantial and become a limiting factor in designing the voltage regulator in the form of area crunch or limit (e.g., there may be a predetermined maximum resistance for “R”).